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22504 tn im no no.7373-1/17 ver.1.01 70201 preliminary overview the lc876132a/24a/16a are 8 bit single chip microcontrollers with the following on-chip functional blocks : ? cpu: operable at a minimum bus cycle time of 100ns ? on-chip rom maximum capacity : lc876132a 32k bytes LC876124A 24k bytes lc876116a 16k bytes ? on-chip ram: 768 bytes ? vfd automatic display controller / driver ? 16 bit timer / counter (can be divided into two 8 bit timers) ? 16 bit timer / pwm (can be divided into two 8 bit timers) ? system clock divider function ? synchronous serial i/o port (with automatic block tran smit / receive function) ? asynchronous / synchronous serial i/o port ? 10-channel 8-bit ad converter ? 13-source 10-vectored interrupt system all of the above functions are fabricated on a single chip. ordering number : enn*7373 8 bit single chip microcontroller with 32k/24k/16k-byte rom and 768-byte ram on chip lc876132a/24a/16a cmos ic package dimensions unit: mm 3174a [ lc876132a/24a/16a ]
lc876132a/24a/16a no.7373-2/17 features (1) read-only memory (rom): lc876132a 32768 8 bits LC876124A 24576 8 bits lc876116a 16384 8 bits (2) random access memory (ram): lc876132a/24a/16a 768 9 bits (3) minimum bus cycle time: 100 ns (10mhz) note: the bus cycle time indicates rom read time. (4) minimum instruction cycle time: 300 ns (10mhz) (5) ports ? input / output ports data direction programmable for each b it individually : 12 (p1n, p70 to p73) data direction programmable in nibble unit : 8 (p0n) (when n-channel open drain output is selected, data can be input in bit unit.) ? vfd output ports large current outputs for digits : 9 (s0 / t0 to s8 / t8) large current outputs for digits / segments : 7 (s9 / t9 to s15 / t15) digit / segment outputs : 8 (s16 to s23) segment outputs : 28 (s24 to s51) other functions input ports : 16 (pcn, pdn) output ports : 8 (pfn) input / output ports : 4 (pgn) ? oscillator pins : 2 (cf1, cf2) ? reset pin : 1 ( res ) ? power supply : 4 (v ss 1, v dd 1 to 3) ? vfd power supply : 1 (vp) (6) vfd automatic display controller ? programmable segment / digit output pattern output can be switched between digit / segment waveform output (pins 9 to 24 can be used for output of digit waveforms). parallel-drive available for large current vfd. ? 16-step dimmer function available (7) timers ? timer 0: 16 bit timer / counter with capture register mode 0: 2 channel 8-bit timer with programmable 8 bit prescaler and 8 bit capture register mode 1: 8 bit timer with 8 bit programmable prescaler and 8 bit capture register + 8 bit counter with 8-bit capture register mode 2: 16 bit timer with 8 bit programmable prescaler and 16 bit capture register mode 3: 16 bit counter with 16 bit capture register ? timer 1: pwm / 16 bit timer toggle output mode 0: 2 channel 8 bit timer (with toggle output) mode 1: 2 channel 8 bit pwm mode 2: 16 bit timer (with toggle output) toggle output also possible using lower 8 bits. mode 3: 16 bit timer (with toggle output) lower 8 bits can be used as pwm output.
lc876132a/24a/16a no.7373-3/17 (8) serial-interface ? sio 0: 8 bit synchronous serial interface 1) lsb first / msb first is selectable 2) internal 8 bit baud-rate generator (maximum transmit clock period 4 / 3 tcyc) 3) continuous automatic data communication (1-256 bits) ? sio 1: 8 bit asynchronous / synchronous serial interface mode 0: synchronous 8 bit serial i o (2-wire or 3-wire, transmit clock 2?512 tcyc) mode 1: asynchronous serial i o (half duplex, 8 data bits, 1 stop bit, baud rate 8?2048 tcyc) mode 2: bus mode 1 (start bit, 8 data bits, transmit clock 2?512 tcyc) mode 3: bus mode 2 (start detection, 8 data bits, stop detection) (9) ad converter ? 8 bits 10 channels (10) remote control receiver circuit (conn ected to p73 / int3 / t0in terminal) ? noise rejection function (noise rejection filter time constant can selected from 1 / 32 / 128 tcyc) (11) watchdog timer ? the watching timer period is determined by an external rc. ? watchdog timer can produce interrupt, system reset (12) interrupts: 13-source, 10-vectored interrupts 1) three priority, low (l), high (h) and hi ghest (x), multiple interrupts are supported. during interrupt handling, an equal or lowe r priority interrupt request is postponed. 2) if interrupt requests to two or more vector addresses occur at once, the higher priority interrupt takes precedence. in the case of equal priority levels, the vect or with the lowest address takes precedence. no. vector selectable level interrupt signal 1 00003h x or l int0 2 0000bh x or l int1 3 00013h h or l int2 / t0l 4 0001bh h or l int3 5 00023h h or l t0h 6 0002bh h or l t1l / t1h 7 00033h h or l sio0 8 0003bh h or l sio1 9 00043h h or l adc 10 0004bh h or l vfd automatic display controller / port0 ? priority level : x > h > l ? for equal priority levels, vector with lowest address takes precedence. (13) subroutine stack levels: 384 levels max. stack is located in ram. (14) multiplication and division ? 16 bits 8 bits (executed in 5 cycles) ? 24 bits 16 bits (executed in 12 cycles) ? 16 bits 8 bits (executed in 8 cycles) ? 24 bits 16 bits (executed in 12 cycles) (15) oscillation circuits ? on-chip rc oscillation circuit for system clock use. ? on-chip cf oscillation circuit for system clock use. (r f built in) ? frequency variable rc oscillation circuit (imbedded) for system clock use.
lc876132a/24a/16a no.7373-4/17 (16) system clock divider function ? able to reduce current consumption available minimum instruction cycle time: 300ns, 600ns, 1.2 s, 2.4 s, 4.8 s, 9.6 s, 19.2 s, 38.4 s, 76.8 s. (using 10mhz main clock) (17) standby function ? halt mode halt mode is used to reduce power consumption. pr ogram execution is stopped. peripheral circuits still operate but vfd display and some serial transfer operations stop. 1) oscillation circuits ar e not stopped automatically. 2) release occurs on system reset or by interrupt. ? hold mode hold mode is used to reduce power consumption. both program execution and peripheral circuits are stopped. 1) cf, rc and crystal oscillation circuits stop automatically. 2) release occurs on any of the following conditions. (1) input to the reset pin goes low (2) a specified level is input at least one of int0, int1, int2 (3) an interrupt condition arises at port 0 (18) factory shipment ? qip80e (19) development tools ? evaluation chip: lc876093 ? emulator: eva62s + ecb876600 (evaluation chip board) + sub876100 + pod80qfp : ice-b877300 + sub876100 + pod80qfp pin assignment lc876132a LC876124A lc876116a top view sanyo : qip80e s38 s39 v dd 3 s40/pf0 s41/pf1 s42/pf2 s43/pf3 s44/pf4 s45/pf5 s46/pf6 s47/pf7 s48/pg0 s49/pg1 s50/pg2 s51/pg3 p10/so0 s15/t15 s14/t14 s13/t13 s12/t12 s11/t11 s10/t10 s9/t9 s8/t8 s7/t7 s6/t6 s5/t5 s4/t4 s3/t3 s2/t2 s1/t1 s0/t0 s37 s36 s35 s34 s33 s32 s31/pd7 s30/pd6 s29/pd5 s28/pd4 s27/pd3 s26/pd2 s25/pd1 s24/pd0 s23/pc7 s22/pc6 s21/pc5 s20/pc4 s19/pc3 s18/pc2 s17/pc1 s16/pc0 v dd 2 vp 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 p11/si0/sb0 p12/sck0 p13/so1 p14/si1/sb1 p15/sck1 p16/t1pwml p17/t1pwmh res v ss 1 cf1 cf2 v dd 1 p00/an0 p01/an1 p02/an2 p03/an3 p04/an4 p05/an5 p06/an6 p07/an7 p70/int0/t0lcp/an8 p71/int1/t0hcp/an9 p72/int2/t0in p73/int3/t0in
lc876132a/24a/16a no.7373-5/17 system block diagram interrupt control stand-by control ir pla rom mrc pc rc cf clock generator bus interface port 0 port 1 sio0 sio1 timer 0 vfd controller int0 - 3 noise rejection filter port 7 adc acc b register c register psw rar ram stack pointer watchdog timer alu timer 1
lc876132a/24a/16a no.7373-6/17 pin description pin name i/o function option v ss 1 - ? power supply (-) no v dd 1 v dd 2 v dd 3 - ? power supply (+) no vp - ? power supply (-) no port0 p00 to p07 i/o ? 8 bit input / output port ? data direction programmable in nibble units ? use of pull-up resistors for p1 to p3 and p4 to p7 can be specified in three bit unit and nibble unit respectively. ? input for hold release ? input for port 0 interrupt ? other function a/d conversion input port: an0 to an7 yes (p00 has no option) port1 p10 to p17 i/o ? 8-bit input / output port ? data direction programmable for each bit ? use of pull-up resistor c an be specified for each bit ? other pin functions p10: sio0 data output p11: sio0 data input / bus input / output p12: sio0 clock input / output p13: sio1 data output p14: sio1 data input / bus input / output p15: sio1 clock input / output p16: timer 1 pwml output p17: timer 1 pwmh output / buzzer output yes ? 4-bit input / output port ? data direction can be specified for each bit ? use of pull-up resist or can be specified ? other functions p70: int0 input / hold release input / timer0l capture input / output for watchdog timer p71: int1 input / hold releas e input / timer0h capture input p72: int2 input / hold release input / time r 0 event input / timer0l capture input / high speed clock counter input p73: int3 input (noise reject ion filter attached input) / time r 0 event input / timer 0h capture input ad input port: an8 (p70), an9 (p71) the following types of interrupt detection are possible: rising falling rising / falling h level l level int0 int1 int2 int3 yes yes yes yes yes yes yes yes no no yes yes yes yes no no yes yes no no port7 p70 to p73 i/o no s0 / t0 to s8 / t8 o ? large current output for vfd display c ontroller digit (can be used for segment) no s9 / t9 to s15 / t15 o ? large current output for vfd disp lay controller segment / digit no s16 to s23 i/o ? output for vfd display controller segment / digit ? other functions: high volt age input port: pc0 to pc7 no s24 to s31 i/o ? output for vfd display controller segment ? other functions: high volt age input port: pd0 to pd7 no s32 to s39 o ? output for vfd displa y controller segment no s40 to s47 o ? output for vfd disp lay controller segment ? other functions: high volt age output port: pf0 to pf7 no s48 to s51 i/o ? output for vfd di splay controller segment ? other functions: high voltage i nput / output port: pg0 to pg3 no res i reset terminal no cf1 i input terminal fo r ceramic oscillator no cf2 o output terminal for ceramic oscillator no
lc876132a/24a/16a no.7373-7/17 port output configuration output configuration and pull-up / pull-down resistor options are shown in the following table. input / output is possible even when port is set to output mode. terminal option applies to: options output format pull-up resistor pull-down resistor p00 - none n-ch open drain none - 1 cmos programmable (note 1) - p01 to p07 1 bit unit 2 nch-open drain none - 1 cmos programmable - p10 to p17 1 bit unit 2 nch-open drain programmable - p70 - none nch-open drain programmable - p71 to p73 - none cmos programmable - s0 / t0 to s6 / t6 - none high voltage pch-open drain - none s7 / t7 to s15 / t15 - none high voltage pch-open drain - fixed s16 to s31 - none high voltage pch-open drain - none s32 to s39 - none high voltage pch-open drain - fixed s40 to s47 - none high voltage pch-open drain - none s48 to s51 - none high voltage pch-open drain - none note 1 pull-up resisters for port 0 can be attached in three-bit unit (p01-03) and nibble unit (p04-07) by the program. * note 1: connect as follows to reduce noise on v dd and increase the back-up time. power supply lsi v dd 1 v dd 2 v ss 1 v dd 3 power supply for vfd
lc876132a/24a/16a no.7373-8/17 absolute maximum ratings / ta=25 c and v ss 1=0v parameter symbol pins conditions v dd [v] min typ max unit supply voltage v dd max v dd 1, v dd 2, v dd 3 v dd 1=v dd 2=v dd 3 -0.3 +6.5 v i (1) cf1, res -0.3 v dd +0.3 input voltage v i (2) vp v dd -45 v dd +0.3 output voltage v o (1) s0 / t0 to s15 / t15 s32 to s47 v dd -45 v dd +0.3 v io (1) ?port 0 ?port 1 ?port 7 -0.3 v dd +0.3 input / output voltage v io (2) s16 to s31, s48 to s51 v dd -45 v dd +0.3 v [high level output current] ioph(1) port 0, 1 ?cmos output selected ?current at each pin -10 ioph(2) port71, 72, 73 current at each pin -3 ioph(3) s0 / t0 to s15 / t15 current at each pin -30 peak output current ioph(4) s16 to s51 current at each pin -15 ioah(1) port 0 total of all pins -30 ioah(2) port 1 total of all pins -30 ioah(3) port 7 total of all pins -5 ioah(4) s0 / t0 to s15 / t15 total of all pins -65 ioah(5) s16 to s27 total of all pins -60 ioah(6) s28 to s39 total of all pins -60 total output current ioah(7) s40 to s51 total of all pins -60 ma [low level output current] iopl(1) port 0, 1 for each pin 20 peak output current iopl(2) port 7 for each pin 5 ioal(1) port 0 total of all pins 60 total output current ioal(2) ports 1, 7 total of all pins 60 ma maximum power consumption pd max qip80e ta = -30 to +70 c 478 mw operating temperature range topr -30 +70 storage temperature range tstg -55 +125 c
lc876132a/24a/16a no.7373-9/17 recommended operating range / ta=-30 c to +70 c, v ss 1=0v parameter symbol pins conditions v dd [v] min typ max unit operating supply voltage range v dd (1) v dd 1=v dd 2=v dd 3 0.294 s tcyc 200 s 4.5 5.5 hold voltage vhd v dd 1 ram and the register data are kept in hold mode. 2.0 5.5 pull-down voltage vp vp 4.5 to 5.5 -35 v dd v ih (1) ?port 0 output disable 4.5 to 5.5 0.3v dd +0.7 v dd v ih (2) ?port 1 ?port 71, 72, 73 ?p70 port input / interrupt output disable 4.5 to 5.5 0.3v dd +0.7 v dd v ih (3) s16 to s31 s48 to s51 output p-channel tr. off 4.5 to 5.5 0.33v d d +1.0 v dd v ih (4) port 70 watchdog timer output disable 4.5 to 5.5 0.9v dd v dd input high voltage v ih (5) cf1, res 4.5 to 5.5 0.75v d d v dd v il (1) ?port 0 output disable 4.5 to 5.5 v ss 0.15v dd +0.4 v il (2) ?port 1 ?port 71, 72, 73 ?p70 port input / interrupt output disable 4.5 to 5.5 v ss 0.1v dd +0.4 v il (3) s16 to s31 s48 to s51 output p-channel tr. off 4.5 to 5.5 v ss 0.2v dd v il (4) port 70 watchdog timer output disabled 4.5 to 5.5 v ss 0.8v dd -1.0 input low voltage v il (5) cf1, res 4.5 to 5.5 v ss 0.25v dd v operation cycle time tcyc 4.5 to 5.5 0.294 200 s ?cf2 open circuit ?system clock divider set to 1/1 ?external clock duty = 50 5% 4.5 to 5.5 0.1 10 external system clock frequency fexcf(1) cf1 ?cf2 open circuit ?system clock divider set to 1/2 4.5 to 5.5 0.2 20 fmcf(1) cf1, cf2 10mhz ceramic resonator oscillation refer to figure 1 4.5 to 5.5 10 fmcf(2) cf1, cf2 4mhz ceramic resonator oscillation refer to figure 1 4.5 to 5.5 4 fmmrc frequency variable rc oscillation 4.5 to 5.5 50 oscillation stabilizing time period (note 1) fmrc rc oscillation 4.5 to 5.5 0.3 1.0 2.0 mhz (note 1) the oscillation constant is shown in table 1 and table 2.
lc876132a/24a/16a no.7373-10/17 electrical characteristics / ta=-30 c to +70 c, v ss 1=0v parameter symbol pins conditions v dd [v] min typ max unit i ih (1) port 0, 1, 7 ?output disabled ?pull-up resister off. ?v in =v dd (including off state leak current of the output tr.) 4.5 to 5.5 1 i ih (2) s16 to s31 s48 to s51 (port c, d, g) when configured as an input port v in =v dd 60 i ih (3) res v in =v dd 4.5 to 5.5 1 input high current i ih (4) cf1 v in =v dd 4.5 to 5.5 15 i il (1) port 0, 1, 7 ?output disabled ?pull-up resister off ?v in =v ss (including off state leak current of the output tr.) 4.5 to 5.5 -1 i il (2) res v in =v ss 4.5 to 5.5 -1 input low current i il (3) cf1 v in =v ss 4.5 to 5.5 -15 a v oh (1) i oh =-1.0ma 4.5 to 5.5 v dd -1 v oh (2) port 0, 1 i oh =-0.1ma 4.5 to 5.5 v dd -0.5 v oh (3) port 7 i oh =-0.4ma 4.5 to 5.5 v dd -1 v oh (4) i oh =-20.0ma 4.5 to 5.5 v dd -1.8 v oh (5) s0 / t0 to s15 / t15 i oh =-1.0ma i oh at any single pin is not over 1ma. 4.5 to 5.5 v dd -1 v oh (6) i oh =-5.0ma 4.5 to 5.5 v dd -1.8 output high voltage v oh (7) s16 to s51 i oh =-1.0ma i oh at any single pin is not over 1ma. 4.5 to 5.5 v dd -1 v ol (1) i ol =9ma 4.5 to 5.5 1.5 v ol (2) port 0, 1 i ol =1.5ma 4.5 to 5.5 0.4 output low voltage v ol (3) port 7 i ol =1ma 4.5 to 5.5 0.4 v pull-up resistor rpu port 0, 1, 7 v oh =0.9v dd 4.5 to 5.5 15 40 70 k ? i off (1) ?output p-ch tr. off ?v out =v ss 4.5 to 5.5 -1 output off-leak current i off (2) s0 / t0 to s6 / s6, s16 to s31 s48 to s51 ?output p-ch tr. off ?v out =v dd -40v 4.5 to 5.5 -30 a resistance of the low level hold tr. rinpd s16 to s31 s48 to s51 ?output p-ch tr. off 4.5 to 5.5 200 high voltage pull-down resistor rpd s7 / t7 to s15 / t15, s32 to s39 ?output p-ch tr. off ?v out =3v ?vp=-30v 5.0 60 100 200 k ? hysteresis voltage vhis(1) ?port 1, 7 ? res 4.5 to 5.5 0.1v dd v pin capacitance cp all pins ?all other terminals connected to v ss . ?f=1mhz ?ta=25 c 4.5 to 5.5 10 pf
lc876132a/24a/16a no.7373-11/17 serial input / output characteristics / ta=-30 c to +70 c, v ss 1=0v parameter symbol pins conditions v dd [v] min typ max unit [serial clock] [input clock] cycle time tsck(1) 4/3 tsckl(1) 2/3 low level pulse width tsckla(1) 2/3 tsckh(1) 2/3 high level pulse width tsckha(1) sck0(p12) refer to figure 5 4.5 to 5.5 3 cycle time tsck(2) 2 low level pulse width tsckl(2) 1 high level pulse width tsckh(2) sck1(p15) refer to figure 5 4.5 to 5.5 1 tcyc [output clock] cycle time tsck(3) 4/3 tcyc tsckl(3) 1/2 low level pulse width tsckla(2) 3/4 tsckh(3) 1/2 high level pulse width tsckha(2) sck0(p12) ?cmos output option ?refer to figure 5 4.5 to 5.5 2 tsck cycle time tsck(4) 2 tcyc low level pulse width tsckl(4) 1/2 high level pulse width tsckh(4) sck1(p15) ?cmos output option ?refer to figure 5 4.5 to 5.5 1/2 tsck [serial input] data set-up time tsdi 0.03 data hold time thdi si0(p11), si1(p14), sb0(p11), sb1(p14) ?measured with respect to si0clk leading edge. ?refer to figure 5 4.5 to 5.5 0.03 s [serial output] output delay time tddo so0(p10), so1(p13), sb0(p11), sb1(p14) ?measured with respect to si0clk trailing edge. ?when port is open drain: time delay from si0clk trailing edge to the so data change. ?refer to figure 5 4.5 to 5.5 1/3 tcyc +0.05 s pulse input conditions / ta=-30 c to +70 c, v ss 1=0v parameter symbol pins conditions v dd [v] min typ max unit tpih(1) tpil(1) int0(p70), int1(p71), int2(p72) ?interrupt acceptable ?events to timer 0 can be input. 4.5 to 5.5 1 tpih(2) tpil(2) int3(p73) (noise rejection ratio set to 1/1.) ?interrupt acceptable ?events to timer 0 can be input. 4.5 to 5.5 2 tpih(3) tpil(3) int3(p73) (noise rejection ratio set to 1/32.) ?interrupt acceptable ?events to timer 0 can be input. 4.5 to 5.5 64 tpih(4) tpil(4) int3(p73) (noise rejection ratio set to 1/128.) ?interrupt acceptable ?events to timer 0 can be input. 4.5 to 5.5 256 tcyc high / low level pulse width tpil(5) res ?reset possible 4.5 to 5.5 200 s
lc876132a/24a/16a no.7373-12/17 ad converter characteristics / ta=-30 c to + 70 c, v ss 1=0v parameter symbol pins conditions v dd [v] min typ max unit resolution n 4.5 to 5.5 8 bit absolute precision et (note2) 4.5 to 5.5 1.5 lsb ad conversion time = 32 tcyc (adcr2=0) (note 3) 15.62 (tcyc= 0.488 s) 97.92 (tcyc= 3.06 s) conversion time tcad ad conversion time = 64 tcyc (adcr2=1) (note 3) 4.5 to 5.5 18.82 (tcyc= 0.294 s) 97.92 (tcyc= 1.53 s) s analog input voltage range vain 4.5 to 5.5 v ss v dd v iainh vain=v dd 4.5 to 5.5 1 analog port input current iainl an0(p00) to an7(p07) an8(p70), an9(p71) vain=v ss 4.5 to 5.5 -1 a (note 2) absolute precision not including quantizing error ( 1/2 lsb). (note 3) conversion time means time from executing ad conversion instruction to loading complete digital value to register. current consumption characteristics / ta=-30 c to +70 c, v ss 1= 0v parameter symbol pins conditions v dd [v] min typ max unit iddop(1) ?fmcf=10mhz for ceramic resonator oscillation ?system clock: cf oscillation ?internal rc oscillation stopped. ?divider set to 1/1 4.5 to 5.5 8 27 iddop(2) ?cf1=20mhz for external clock ?system clock: cf oscillation ?internal rc oscillation stopped. ?divider set to 1/2 4.5 to 5.5 8.5 28 iddop(3) ?fmcf=4mhz ceramic resonator oscillation ?system clock: cf oscillation ?internal rc oscillation stopped. ?divider set to 1/1 4.5 to 5.5 3.5 15 iddop(4) ?fmcf=0hz (no oscillation) ?system clock: rc oscillation ?divider set to 1/2 4.5 to 5.5 1 8.5 current consumption during basic operation (note 4) iddop(5) v dd 1=v dd 2=v dd 3 ?fmcf=0hz (no oscillation) ?internal rc oscillation stopped. ?system clock: rc oscillation ?divider set to 1/2 4.5 to 5.5 2.0 10.5 ma continued on next page.
lc876132a/24a/16a no.7373-13/17 continued from preceding page. parameter symbol pins conditions v dd [v] min typ max unit iddhalt(1) halt mode ?fmcf=10mhz for ceramic resonator oscillation ?system clock : cf oscillation ?internal rc oscillation stopped. ?divider: 1/1 4.5 to 5.5 iddhalt(2) halt mode ?cf1=20mhz for external clock ?system clock : cf oscillation ?internal rc oscillation stopped. ?divider: 1/2 4.5 to 5.5 iddhalt(3) halt mode ?fmcf=4mhz for ceramic resonator oscillation ?system clock : cf oscillation ?internal rc oscillation stopped. ?divider: 1/1 4.5 to 5.5 ma current consumption halt mode (note 4) iddhalt(4) v dd 1=v dd 2=v dd 3 halt mode ?fmcf=0hz (when oscillation stops.) ?system clock : rc oscillation ?divider: 1/2 4.5 to 5.5 a current consumption hold mode iddhold(1) v dd 1 hold mode ?cf1=v dd or open circuit (when using external clock) 4.5 to 5.5 a (note 4) the currents of the output transistors and the pull-up mos transistors are ignored. main system clock oscillation circuit characteristics the characteristics in the table bellow is based on the following conditions: 1. use the standard evalua tion board sanyo has provided. 2. use the peripheral parts with indicated value externally. 3. the peripheral parts value is a recommended value of oscillator manufacturer. table 1. main system clock oscillation circuit characteristics using ceramic resonator circuit parameters oscillation stabilizing time frequency manufacturer oscillator c1 c2 rd1 operating supply voltage range typ max notes cstls10m0g53-b0 (15pf) (15pf) 0 ? 4.5 to 5.5v 0.03ms 0/25ms with c1, c2 10mhz murata cstcc10m0g53-r0 (15pf) (15pf) 100 ? 4.5 to 5.5v 0.03ms 0/25ms with c1, c2 cstls4m00g53-r0 (15pf) (15pf) 330 ? 4.5 to 5.5v 0.03ms 0/25ms with c1, c2 murata cstcr4m00g53-r0 (15pf) (15pf) 330 ? 4.5 to 5.5v 0.05ms 0.3ms with c1, c2 pbrc4.00hr (33pf) (33pf) 0 ? 4.5 to 5.5v 0.15ms 1.0ms with c1, c2 4mhz kyosera kbr-4.0mkc (33pf) (33pf) 0 ? 4.5 to 5.5v 0.15ms 1.0ms with c1, c2 the oscillation stabilizing time is a period until the oscillation becomes stable after v dd becomes higher than minimum operating voltage. (refer to figure 3)
lc876132a/24a/16a no.7373-14/17 (notes) ? since the circuit pattern affects the oscillation fre quency, place the oscillation-related parts as close tothe oscillation pins as possible with the shortest possible pattern length. figure 1. ceramic oscillation circuit figure 2. ac timing measurement point c1 c2 cf cf2 cf1 rd1 0.5v dd
lc876132a/24a/16a no.7373-15/17 reset time and oscillation stable time hold release signal and oscillation stable time figure 3. oscillation stabilization time power supply res internal rc resonator oscillation cf1, cf2 operation mode reset time tmscf unfixed reset instruction execution mode v dd v dd limit 0v internal rc resonator oscillation cf1, cf2 operation mode hold release signal without hold release signal hold release signal valid tmscf hold halt
lc876132a/24a/16a no.7373-16/17 figure 4. reset circuit figure 5. serial input / output test condition (note) set c res , r res values such that reset time exceeds 200 s. c res v dd r res res sioclk datain dataout di0 di1 di2 di3 di4 di5 di6 di7 di8 do0 do1 do2 do3 do4 do5 do6 do7 do8 data ram transmission period (only sio0) sioclk datain dataout tsck tsckl tsckh tsdi thdi tddo sioclk datain dataout tddo tsdi thdi tsckla tsckha data ram transmission period (only sio0)
lc876132a/24a/16a no.7373-17/17 figure 6. pulse input timing condition ps tpil tpih

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